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authorKyösti Mälkki <kyosti.malkki@gmail.com>2015-03-20 08:51:57 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-04-28 08:01:46 +0200
commite993ec7948d874d81c984323b5b00389420a4e65 (patch)
tree46a75016a72513728bfa53f16deade9e26020169 /src/drivers
parentb85a87b7d6f9f12d5c71c32741c8af731ed6be7e (diff)
downloadcoreboot-e993ec7948d874d81c984323b5b00389420a4e65.tar.xz
OxPCIe: Fix UART base addresses
The offset of 0x2000 was for a configuration with two separate OxPCIe chips. The setup we support is a single chip with 8 UART pors. Change-Id: If4be046a14464af7b90b86aca5464c6b3400dffc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8780 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/drivers')
-rw-r--r--src/drivers/uart/oxpcie_early.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c
index 9daafc5fd9..d560513eb7 100644
--- a/src/drivers/uart/oxpcie_early.c
+++ b/src/drivers/uart/oxpcie_early.c
@@ -30,7 +30,6 @@
static unsigned int oxpcie_present CAR_GLOBAL;
static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000;
-static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000;
int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base)
{
@@ -79,10 +78,8 @@ static int oxpcie_uart_active(void)
uintptr_t uart_platform_base(int idx)
{
- if (idx == 0 && oxpcie_uart_active())
- return uart0_base;
- if (idx == 1 && oxpcie_uart_active())
- return uart1_base;
+ if ((idx >= 0) && (idx < 8) && oxpcie_uart_active())
+ return uart0_base + idx * 0x200;
return 0;
}
@@ -90,7 +87,6 @@ uintptr_t uart_platform_base(int idx)
void oxford_remap(u32 new_base)
{
uart0_base = new_base + 0x1000;
- uart1_base = new_base + 0x2000;
}
void uart_fill_lb(void *data)