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authorFurquan Shaikh <furquan@google.com>2020-03-05 08:06:27 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-03-06 08:06:02 +0000
commite0060a80f0b662f9e4693785baaac16acb96632b (patch)
tree5ead7efd34beebf385546c405123cc19d57b94c3 /src/ec/google/chromeec/Makefile.inc
parent04b02069e26484caf2737a863404daf4a438714b (diff)
downloadcoreboot-e0060a80f0b662f9e4693785baaac16acb96632b.tar.xz
ec/google/chromeec: Fix dev ops for chromeec
CB:38541 ("ec/google/chromeec: Add SSDT generator for ChromeOS EC") added a new device_operations structure for chromeec for handling ACPI SSDT generation. However, this resulted in the original device_operations which handled lpc read resources to be skipped. This change fixes the above regression by combining the device operations for reading resources and ACPI SSDT generation into a single structure and retains the old logic for enabling of pnp devices. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3a242f4b15603f957e0e81d121e5766fccf3c28d Reviewed-on: https://review.coreboot.org/c/coreboot/+/39321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/ec/google/chromeec/Makefile.inc')
-rw-r--r--src/ec/google/chromeec/Makefile.inc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc
index 2833c87d33..590b131355 100644
--- a/src/ec/google/chromeec/Makefile.inc
+++ b/src/ec/google/chromeec/Makefile.inc
@@ -28,7 +28,7 @@ verstage-y += ec.c crosec_proto.c vstore.c
verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
-ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_chip.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_acpi.c
ramstage-$(CONFIG_VBOOT) += vboot_storage.c
smm-$(CONFIG_VBOOT) += vboot_storage.c