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| author | Shaunak Saha <shaunak.saha@intel.com> | 2016-11-02 10:52:23 -0700 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2016-11-09 21:02:27 +0100 |
| commit | 40d7a454a2ebc7d6a69c51cdd5be7924ea0d0191 (patch) | |
| tree | a578dbe271501a0d529e5df525d1ca67928e46ef /src/include/cpu/intel | |
| parent | f22b26ad86d3cdb7ea89cf5f0d7df76cd8575194 (diff) | |
| download | coreboot-40d7a454a2ebc7d6a69c51cdd5be7924ea0d0191.tar.xz | |
cpu/intel: Add MSR to support enabling turbo frequency
This patch adds definition FREQ_LIMIT_RATIO MSR. FREQ_LIMIT_RATIO
register allows to determine the ratio limits to be used to limit
frequency.
BUG=chrome-os-partner:58158
BRANCH=None
Change-Id: I50a792accbaab1bff313fd00574814d7dbba1f6b
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/17211
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/include/cpu/intel')
| -rw-r--r-- | src/include/cpu/intel/speedstep.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 09906df324..40234d5fca 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -46,7 +46,7 @@ #define MSR_PMG_IO_BASE_ADDR 0xe3 #define MSR_PMG_IO_CAPTURE_ADDR 0xe4 #define MSR_EXTENDED_CONFIG 0xee - +#define FREQ_LIMIT_RATIO 0x1AD typedef struct { uint8_t dynfsb : 1; /* whether this is SLFM */ |