summaryrefslogtreecommitdiff
path: root/src/include
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-12-28 16:54:54 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-01-08 15:33:47 +0000
commitc641f7ed9f9083f73ddb69676a74d7e205351baa (patch)
tree7a81b9621e6c667b0c0a5de268cb7ce08e6c972d /src/include
parentee2e936f4059d8aad4161d44915a05271df1aaae (diff)
downloadcoreboot-c641f7ed9f9083f73ddb69676a74d7e205351baa.tar.xz
cpu/intel/car: Prepare for C_ENVIRONMENT_BOOTBLOCK
Pass timestamps and BIST to romstage using the same signature as C_ENVIRONMENT_BOOTBLOCK will. Change-Id: Ic90da6b1b5ac3b56c69b593ba447ed8e05c8a4e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/cpu/intel/romstage.h4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h
index 726a184eb1..47cd169e6a 100644
--- a/src/include/cpu/intel/romstage.h
+++ b/src/include/cpu/intel/romstage.h
@@ -7,8 +7,4 @@ void mainboard_romstage_entry(unsigned long bist);
void platform_enter_postcar(void);
-/* romstage_main is called from the cache-as-ram assembly file to prepare
- * CAR stack guards.*/
-asmlinkage void *romstage_main(unsigned long bist);
-
#endif /* _CPU_INTEL_ROMSTAGE_H */