mb/asus/p8h61-m_pro: Add new mainboard

Tested with GRUB 2.02 as a payload, booting Arch Linux as
well as Debian. This code is based on the output of autoport
as well as other mainboards supported in coreboot already.

Working:
 - Serial port I/O
 - S3 suspend/resume. Untested with SeaBIOS since it failed
   to resume on a similar board. It is likely to be due to
   low memory corruption, but I have not worked on it.
 - USB ports and headers
 - USB3 ports attached to the ASM1042 controller. SeaBIOS can
   boot from them, and it is likely GRUB can detect devices on
   those ports as well. The chip has a small SPI flash nearby,
   which seems to hold an Option ROM.
 - Gigabit Ethernet
 - Integrated graphics (libgfxinit)
 - VGA BIOS for integrated graphics init
 - PCIe x16 graphics
 - PCIe x1
 - SATA controller
 - Hardware Monitor
 - Fan Control (fancontrol on linux works well)
 - Native raminit
 - flashrom, using the internal programmer. Tested with coreboot,
   as well as with the vendor firmware.
 - NVRAM settings. Only debug_level has been tested.

Untested:
 - DVI port. It can detect a "fake" display, that is, an
   EEPROM connected to the DVI port. Thus, gma-mainboard.ads
   has been setup accordingly.
 - PS/2 port.
 - Audio: Only rear output (green) has been tested.
 - EHCI debug.
 - Parallel port header.
 - Non-Linux OSes
 - ACPI thermal zone and fan control (probably not working)

Not working:
 - Booting from devices attached to the ASM1061 controller.
   Devices on ports work fine once Linux has loaded.
 - Any SATA devices with Tianocore (payload issue)

Change-Id: I7e89ebe43a2e1ff0308f4876e98bbf2f5a0d85f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/26419
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 84 insertions, 0 deletions

diff --git a/src/mainboard/asus/p8h61-m_pro/romstage.c b/src/mainboard/asus/p8h61-m_pro/romstage.c
new file mode 100644
index 0000000000..a6785ed418
--- /dev/null
+++ b/src/mainboard/asus/p8h61-m_pro/romstage.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Angel Pons <th3fanbus@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6776/nct6776.h>
+
+#define GLOBAL_DEV PNP_DEV(0x2e, 0)
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
+#define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI)
+
+void pch_enable_lpc(void)
+{
+	/* Enable the Super IO */
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN |
+			KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);
+}
+
+void mainboard_rcba_config(void)
+{
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 0, 0 },
+	{ 1, 0, 0 },
+	{ 1, 0, 1 },
+	{ 1, 0, 1 },
+	{ 1, 0, 2 },
+	{ 1, 0, 2 },
+	{ 1, 0, 3 },
+	{ 1, 0, 3 },
+	{ 1, 0, 4 },
+	{ 1, 0, 4 },
+	{ 1, 0, 6 },
+	{ 1, 0, 5 },
+	{ 1, 0, 5 },
+	{ 1, 0, 6 },
+};
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+void mainboard_config_superio(void)
+{
+	/* Enable UART */
+	nuvoton_pnp_enter_conf_state(GLOBAL_DEV);
+
+	/* Select SIO pin states. */
+	pnp_write_config(GLOBAL_DEV, 0x1c, 0x83);
+	pnp_write_config(GLOBAL_DEV, 0x24, 0x30);
+	pnp_write_config(GLOBAL_DEV, 0x27, 0x40);
+	pnp_write_config(GLOBAL_DEV, 0x2a, 0x20);
+
+	/* Power RAM in S3. */
+	pnp_set_logical_device(ACPI_DEV);
+	pnp_write_config(ACPI_DEV, 0xe4, 0x10);
+
+	pnp_set_logical_device(SERIAL_DEV);
+
+	nuvoton_pnp_exit_conf_state(GLOBAL_DEV);
+
+	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+}