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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2016-07-26 01:54:34 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-02 23:35:49 +0200 |
| commit | cc5be8b72ba5b072030fdd1d382d7156da43114f (patch) | |
| tree | cb94bc583e87b6c58bdf675fdec363003d316227 /src/mainboard/emulation/spike-riscv | |
| parent | aded214e74bcb63990d69551bec7ab03c6785b08 (diff) | |
| download | coreboot-cc5be8b72ba5b072030fdd1d382d7156da43114f.tar.xz | |
arch/riscv: Add include/arch/barrier.h
mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/.
It is currently provided by atomic.h, but I think it fits better into
barrier.h.
The "fence" instruction represents a full memory fence, as opposed to
variants such as "fence r, rw" which represent a partial fence. An
operating system might want to use precisely the right fence, but
coreboot doesn't need this level of performance at the cost of
simplicity.
Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15830
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv')
| -rw-r--r-- | src/mainboard/emulation/spike-riscv/spike_util.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c index 358cb4428e..f0f5301814 100644 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ b/src/mainboard/emulation/spike-riscv/spike_util.c @@ -26,6 +26,7 @@ */ #include <spike_util.h> +#include <arch/barrier.h> #include <arch/errno.h> #include <atomic.h> #include <string.h> |