coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2020-09-12	include/console/uart: make index parameter unsigned	Felix Held
2020-06-13	treewide: Add Kconfig variable MEMLAYOUT_LD_FILE	Furquan Shaikh
2020-05-28	mb/emulation: Remove fake devicetree.cb components	Kyösti Mälkki
2020-05-18	mainboard///*.cb: Remove leading blank lines from SPDX header	Elyes HAOUAS
2020-05-18	mainboard///Kconfig*: Remove leading blank lines from SPDX header	Elyes HAOUAS
2020-05-18	src: Remove leading blank lines from SPDX header	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-09	src/: Replace GPL boilerplate with SPDX header	Patrick Georgi
2020-04-04	mainboard/emulation: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	mainboard/[a-f]*: Remove copyright notices	Patrick Georgi
2019-12-11	fmap: Make FMAP_CACHE mandatory if it is configured in	Julius Werner
2019-12-06	mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.	Philipp Hug
2019-11-23	Kconfig: comply to Linux 5.3's Kconfig language rules	Patrick Georgi
2019-11-01	mb/emulation/*-riscv: Initialize cbmem in romstage	Arthur Heymans
2019-10-27	src: Use 'include <boot/coreboot_tables.h>' when appropriate	Elyes HAOUAS
2019-03-04	arch/io.h: Drop unnecessary include	Kyösti Mälkki
2019-02-13	riscv: Add initial support for 32bit boards	Philipp Hug
2018-12-05	mb/emulation/spike-riscv: Implement mtime_init	Jonathan Neuschäfer
2018-11-28	mb///Kconfig: Remove useless comment	Elyes HAOUAS
2018-10-29	Documentation/mainboard: Add emulation/spike-riscv.md	Jonathan Neuschäfer
2018-10-22	mainboard/: Select MISSING_BOARD_RESET appropriately	Nico Huber
2018-10-06	mb/emulation/*-riscv: Remove "UCB" from RISC-V board names	Jonathan Neuschäfer
2018-06-09	mainboard: Get rid of device_t in ramstage	Elyes HAOUAS
2018-06-02	src/mainboard: Add and update license headers	Martin Roth
2018-04-27	RISC-V boards: Remove PAGETABLES section from memlayout.ld	Jonathan Neuschäfer
2018-04-25	util/riscvtools: Rename to util/riscv/	Jonathan Neuschäfer
2018-02-20	mb/emu/spike-riscv: Move usage instructions into Kconfig help	Jonathan Neuschäfer
2017-11-07	RISC-V boards: Stop using the config string	Jonathan Neuschäfer
2017-09-27	mb/emu/*-riscv: Remove outdated memory map	Jonathan Neuschäfer
2017-06-12	mb/emulation/spike-riscv: Update UART address	Jonathan Neuschäfer
2017-02-23	mb/emulation/*-riscv: Don't select ARCH_BOOTBLOCK_RISCV	Jonathan Neuschäfer
2017-01-16	riscv/spike: Remove obsolete DRAM_SIZE_MB setting	Jonathan Neuschäfer
2016-11-12	riscv: start to use the configstring functions	Ronald G. Minnich
2016-11-07	riscv: Unify SBI call implementations under arch/riscv/	Jonathan Neuschäfer
2016-10-24	RISCV: Clean up the common architectural code	Ronald G. Minnich
2016-10-15	riscv: Use the generic src/lib/bootblock.c	Jonathan Neuschäfer
2016-10-15	riscv: Clean up {qemu,spike}_util	Jonathan Neuschäfer
2016-10-15	riscv and power8: Convert printk/while(1) to die	Jonathan Neuschäfer
2016-08-23	arch/riscv: Implement the SBI again	Jonathan Neuschäfer
2016-08-18	Kconfig: lay groundwork for not assuming SPI flash boot device	Aaron Durbin
2016-08-02	arch/riscv: Add include/arch/barrier.h	Jonathan Neuschäfer
2016-07-14	spike-riscv: Look for the CBFS in RAM	Jonathan Neuschäfer
2016-07-14	spike-riscv: Register RAM resource at 0x80000000	Jonathan Neuschäfer
2016-07-12	spike-riscv: Remove HTIF related code	Jonathan Neuschäfer
2016-06-21	riscv-spike: Move coreboot to 0x80000000 (2GiB)	Jonathan Neuschäfer
2016-06-17	Define RAMTOP for x86 only	Kyösti Mälkki
2016-06-12	riscv-spike: Replace custom UART with a memory-mapped 8250	Jonathan Neuschäfer
2016-04-28	Add board URLs for the RISC-V boards	Jonathan Neuschäfer
2016-04-28	Fix "Spike RISCV" board name	Jonathan Neuschäfer
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi