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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2018-04-17 14:00:34 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-04-27 09:07:43 +0000
commit5135f1184df2809e4faeb4ecdcad4bc1cb5af70b (patch)
treee6deecf5593037529f32eb5cd418c9aaed7f1b93 /src/mainboard/emulation/spike-riscv
parent062c729c9b7a405c42b020480a1a76f24c5cb868 (diff)
downloadcoreboot-5135f1184df2809e4faeb4ecdcad4bc1cb5af70b.tar.xz
RISC-V boards: Remove PAGETABLES section from memlayout.ld
RISC-V doesn't set up page tables anymore, since commit b26759d703 ("arch/riscv: Don't set up virtual memory"). Change-Id: Id1e759b63fb0bc88ab256994d3849d16814affa0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/emulation/spike-riscv')
-rw-r--r--src/mainboard/emulation/spike-riscv/memlayout.ld2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld
index 8596723796..bae414ffd5 100644
--- a/src/mainboard/emulation/spike-riscv/memlayout.ld
+++ b/src/mainboard/emulation/spike-riscv/memlayout.ld
@@ -24,7 +24,7 @@ SECTIONS
DRAM_START(START)
BOOTBLOCK(START, 64K)
STACK(START + 8M, 4K)
- PAGETABLES(START + 8M + 4K, 60K)
+ /* hole at (START + 8M + 4K, 60K) */
ROMSTAGE(START + 8M + 64K, 128K)
PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
RAMSTAGE(START + 8M + 200K, 256K)