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| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-04-30 07:07:22 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2009-04-30 07:07:22 +0000 |
| commit | 12aba82e55c02470ed80b7682efa8b4e8f702bc1 (patch) | |
| tree | f48156a0a625fdd9d7358e6a172a5cdb343ca9a7 /src/mainboard/gigabyte/m57sli | |
| parent | a43ee75d9a7dc859292b186f22ac0550f149a0a3 (diff) | |
| download | coreboot-12aba82e55c02470ed80b7682efa8b4e8f702bc1.tar.xz | |
Refactor copy_and_run so that it uses a single code base instead of
3 (with one of them way too much assembler code).
On the way, I had to make some changes to the way the code is built,
which is an effort I want to expand over time.
Right now, large portions of the in-ROM part of coreboot is compiled as
a single file, with lots of .c files including other .c files.
That has its justification for pre-raminit code, but it also affects
lots of post-raminit code (memcpy doesn't really make sense before
raminit, or at least CAR)
The coreboot_apc code (AMD boards) gained some .c includes because I
don't know that part of the code enough to really rework it and only
have limited possibilities to test it. The includes should give an
identical situation for this part of the code.
This change was posted as set of 6 patches to the list, but they
were mostly split for review purposes, hence commit them all at once.
They can still be backed up using the patch files, if necessary.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/gigabyte/m57sli')
| -rw-r--r-- | src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c index fb52c86c24..5462c31891 100644 --- a/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c +++ b/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c @@ -46,6 +46,7 @@ #define DBGP_DEFAULT 7 #include <stdint.h> +#include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <arch/io.h> @@ -82,10 +83,6 @@ #include "cpu/x86/bist.h" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" |