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| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2019-02-08 00:29:00 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-02-15 16:27:29 +0000 |
| commit | fe1b40b1ddbdb1ca2fdc4d66d4c3a1d7c758b76a (patch) | |
| tree | b8279042a260f98decdb9cf227cd42ec58de208c /src/mainboard/google/hatch/variants/baseboard/devicetree.cb | |
| parent | a5cc0cfbf5f1facb8906340301399920cf0a48e2 (diff) | |
| download | coreboot-fe1b40b1ddbdb1ca2fdc4d66d4c3a1d7c758b76a.tar.xz | |
mb/google/hatch: Enable DPTF functionality
Enable DPTF functionality on hatch platform.
Change-Id: If9ef74364616f95b27b73c39fea42d2623d78ae2
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/hatch/variants/baseboard/devicetree.cb')
| -rw-r--r-- | src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index eb528f25f1..aaef66365b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -57,6 +57,11 @@ chip soc/intel/cannonlake register "speed_shift_enable" = "1" # Enable S0ix register "s0ix_enable" = "1" + # Enable DPTF + register "dptf_enable" = "1" + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "44" + register "Device4Enable" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 |