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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-06-23 13:07:10 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-27 21:32:26 +0000 |
| commit | 6f174ee0dda132d1d8e18398a79ecba99094a068 (patch) | |
| tree | cbf7974cc194188fb26f24e274c100f9378ac355 /src/mainboard/google/kahlee/OemCustomize.c | |
| parent | a9d3d65a924ce765a481337ca22d36f5ab351ced (diff) | |
| download | coreboot-6f174ee0dda132d1d8e18398a79ecba99094a068.tar.xz | |
google/kahlee: Update for single DIMM
Update for a single DIMM with an SPD at address A0.
Change-Id: I646f079c99cbaffd7094773243600c3030308325
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19833
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/kahlee/OemCustomize.c')
| -rw-r--r-- | src/mainboard/google/kahlee/OemCustomize.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 3893e5dbcb..2b3ac292f6 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -20,7 +20,7 @@ static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), MOTHER_BOARD_LAYERS(LAYERS_6), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, |