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authorVladimir Serbinenko <phcoder@gmail.com>2014-10-25 15:20:55 +0200
committerVladimir Serbinenko <phcoder@gmail.com>2014-11-08 13:41:48 +0100
commit5b044ae6077bfd6bbc162741cc5b3086dbf56d34 (patch)
treee9c19449268b2b4af80bc8aa64eced8ff8e950a6 /src/mainboard/google/link/devicetree.cb
parent986e85c098f6a68c2f26d1b5f81bebaff4207e28 (diff)
downloadcoreboot-5b044ae6077bfd6bbc162741cc5b3086dbf56d34.tar.xz
bd82x6x: Move to common FADT.
Change-Id: I04ed600796c55f5af4f0a07687f676e6484a9830 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7200 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/google/link/devicetree.cb')
-rw-r--r--src/mainboard/google/link/devicetree.cb3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
index 8f0ed3c7e8..15aa432e64 100644
--- a/src/mainboard/google/link/devicetree.cb
+++ b/src/mainboard/google/link/devicetree.cb
@@ -72,6 +72,9 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
+ register "c2_latency" = "1"
+ register "p_cnt_throttling_supported" = "0"
+
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R