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authorLijian Zhao <lijian.zhao@intel.com>2018-12-17 10:03:05 -0800
committerDuncan Laurie <dlaurie@chromium.org>2019-01-16 02:07:56 +0000
commit59de870aa3f2bb758e6bb1deecc49e484cd9834a (patch)
tree67b3fba5a9b77209bc20e659ca93da5b5e0f2644 /src/mainboard/google/sarien
parent51122920e81bdeb5fe7bc68e03128a9b4983cdb9 (diff)
downloadcoreboot-59de870aa3f2bb758e6bb1deecc49e484cd9834a.tar.xz
mb/google/sarien: Set Vref Config to 2
Accoding to desciption in FSP header, Vref Configuration will be set to 2 if VREF_CA to CH_A and VREF_DQ_B to CH_B. BUG=N/A TEST=Build and boot up on Arcada platform. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I02e16e141b81d766a6060ca08283f432abd96647 Reviewed-on: https://review.coreboot.org/c/30280 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/sarien')
-rw-r--r--src/mainboard/google/sarien/romstage.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c
index 7284d5552b..95af0bc18c 100644
--- a/src/mainboard/google/sarien/romstage.c
+++ b/src/mainboard/google/sarien/romstage.c
@@ -37,6 +37,9 @@ static const struct cnl_mb_cfg memcfg = {
/* Disable Early Command Training */
.ect = 0,
+
+ /* Base on board design */
+ .vref_ca_config = 2,
};
void mainboard_memory_init_params(FSPM_UPD *memupd)