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authorShamile Khan <shamile.khan@intel.com>2018-02-22 13:45:39 -0800
committerMartin Roth <martinroth@google.com>2018-03-08 16:46:11 +0000
commitc5f354b97bb6ddff736c12626b5399da5a5faafc (patch)
treea7ba0d50e7fa8bdaa102750431d2c21dc6fe4537 /src/mainboard/google
parentbbb2a9551dbdb31e35fbaa403f9ebfe7a2654c02 (diff)
downloadcoreboot-c5f354b97bb6ddff736c12626b5399da5a5faafc.tar.xz
mb/google/octopus: Add device tree settings
Change-Id: Id45409a9561671237410dd2f8f0bbfe61ff33562 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/23846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google')
-rw-r--r--src/mainboard/google/octopus/variants/baseboard/devicetree.cb162
1 files changed, 162 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
index 64e07c303e..9d267cf445 100644
--- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb
@@ -2,4 +2,166 @@ chip soc/intel/apollolake
device cpu_cluster 0 on
device lapic 0 on end
end
+
+ # EMMC TX DATA Delay 1
+ # Refer to EDS-Vol2-16.33.
+ # [14:8] steps of delay for HS400, each 125ps.
+ # [6:0] steps of delay for SDR104/HS200, each 125ps.
+ register "emmc_tx_data_cntl1" = "0x0C3A"
+
+ # EMMC TX DATA Delay 2
+ # Refer to EDS-Vol2-16.34.
+ # [30:24] steps of delay for SDR50, each 125ps.
+ # [22:16] steps of delay for DDR50, each 125ps.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps.
+ # [6:0] steps of delay for SDR12, each 125ps.
+ register "emmc_tx_data_cntl2" = "0x28272929"
+
+ # EMMC RX CMD/DATA Delay 1
+ # Refer to EDS-Vol2-16.35.
+ # [30:24] steps of delay for SDR50, each 125ps.
+ # [22:16] steps of delay for DDR50, each 125ps.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps.
+ # [6:0] steps of delay for SDR12, each 125ps.
+ register "emmc_rx_cmd_data_cntl1" = "0x003B263B"
+
+ # EMMC RX CMD/DATA Delay 2
+ # Refer to EDS-Vol2-16.37.
+ # [17:16] stands for Rx Clock before Output Buffer
+ # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
+ # [6:0] steps of delay for HS200, each 125ps.
+ register "emmc_rx_cmd_data_cntl2" = "0x10008"
+
+ # EMMC RX STROBE Delay
+ # Refer to EDS-Vol2-16.36.
+ # [16] Enable Auto Tuning for HS400 Strobe Path
+ # [14:8] steps of delay for HS400 Mode 1, each 125ps.
+ # [6:0] steps of delay for HS400 Mode 2, each 125ps.
+ register "emmc_rx_strobe_cntl" = "0x0a0a"
+
+ # EMMC TX COMMAND Delay
+ # Refer to EDS-Vol2-16.32.
+ # [14:8] steps of delay for DDR Mode, each 125ps.
+ # [6:0] steps of delay for SDR Mode, each 125ps.
+ register "emmc_tx_cmd_cntl" = "0x1305"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route, i.e., if this route changes then the affected GPE
+ # offset bits also need to be changed. This sets the PMC register
+ # GPE_CFG fields.
+ register "gpe0_dw1" = "PMC_GPE_NW_63_32"
+ register "gpe0_dw2" = "PMC_GPE_N_95_64"
+ register "gpe0_dw3" = "PMC_GPE_NW_31_0"
+
+ # Minimum SLP S3 assertion width 28ms.
+ register "slp_s3_assertion_width_usecs" = "28000"
+
+ # Enable lpss s0ix
+ register "lpss_s0ix_enable" = "1"
+
+ # digitizer at 400kHz
+ register "i2c[0]" = "{
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 152,
+ .fall_time_ns = 30,
+ }"
+
+ # trackpad at 400kHz
+ register "i2c[6]" = "{
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 114,
+ .fall_time_ns = 164,
+ .data_hold_time_ns = 350,
+ }"
+
+ # touchscreen at 400kHz
+ register "i2c[7]" = "{
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 76,
+ .fall_time_ns = 164,
+ }"
+
+ device domain 0 on
+ device pci 00.0 on end # - Host Bridge
+ device pci 00.1 on end # - DPTF
+ device pci 00.2 on end # - NPK
+ device pci 02.0 on end # - Gen
+ device pci 03.0 on end # - Iunit
+ device pci 0c.0 on end # - CNVi
+ device pci 0d.0 on end # - P2SB
+ device pci 0d.1 on end # - PMC
+ device pci 0d.2 on end # - Fast SPI
+ device pci 0d.3 on end # - Shared SRAM
+ device pci 0e.0 on end # - Audio
+ device pci 0f.0 on end # - Heci1
+ device pci 0f.1 on end # - Heci2
+ device pci 0f.2 on end # - Heci3
+ device pci 11.0 off end # - ISH
+ device pci 12.0 off end # - SATA
+ device pci 13.0 on end # - PCIe-A 0 Onboard M2 Slot(Wifi)
+ device pci 13.1 off end # - PCIe-A 1
+ device pci 13.2 off end # - PCIe-A 2
+ device pci 13.3 off end # - PCIe-A 3
+ device pci 14.0 off end # - PCIe-B 0
+ device pci 14.1 off end # - PCIe-B 1
+ device pci 15.0 on end # - XHCI
+ device pci 15.1 off end # - XDCI
+ device pci 16.0 on
+ chip drivers/i2c/hid
+ register "generic.hid" = ""WCOM50C1""
+ register "generic.desc" = ""WCOM Digitizer""
+ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_139_IRQ)"
+ register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_140)"
+ register "generic.has_power_resource" = "1"
+ register "hid_desc_reg_offset" = "0x1"
+ device i2c 0x9 on end
+ end
+ end # - I2C 0
+ device pci 16.1 on end # - I2C 1
+ device pci 16.2 on end # - I2C 2
+ device pci 16.3 on end # - I2C 3
+ device pci 17.0 off end # - I2C 4
+ device pci 17.1 on end # - I2C 5
+ device pci 17.2 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_135_IRQ)"
+ register "wake" = "GPE0_DW2_02"
+ register "probed" = "1"
+ device i2c 15 on end
+ end
+ end # - I2C 6
+ device pci 17.3 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0001""
+ register "desc" = ""ELAN Touchscreen""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)"
+ register "probed" = "1"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)"
+ register "reset_delay_ms" = "20"
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_213)"
+ register "enable_delay_ms" = "1"
+ register "has_power_resource" = "1"
+ device i2c 10 on end
+ end
+ end # - I2C 7
+ device pci 18.0 on end # - UART 0
+ device pci 18.1 off end # - UART 1
+ device pci 18.2 on end # - UART 2
+ device pci 18.3 off end # - UART 3
+ device pci 19.0 on end # - SPI 0
+ device pci 19.1 off end # - SPI 1
+ device pci 19.2 on end # - SPI 2
+ device pci 1a.0 on end # - PWM
+ device pci 1c.0 on end # - eMMC
+ device pci 1e.0 off end # - SDIO
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # - ESPI
+ device pci 1f.1 on end # - SMBUS
+ end
end