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authorNico Huber <nico.h@gmx.de>2018-05-26 17:47:42 +0200
committerNico Huber <nico.h@gmx.de>2018-05-31 15:08:48 +0000
commitb4953a93aa855afcf801d6f7d48df18f31ee2598 (patch)
tree169121e3fe449dca2a8707c510cf44434df9f28b /src/mainboard/intel/bayleybay_fsp
parentc51df93ccfefb1a5d1dd763d5b8f400c928593a0 (diff)
downloadcoreboot-b4953a93aa855afcf801d6f7d48df18f31ee2598.tar.xz
cpu/x86/mtrr: Get rid of CACHE_ROM_SIZE_OVERRIDE
As far as I can see this Kconfig option was used wrong ever since it was added. According to the commit message of 107f72e (Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary to prevent overlapping with CAR. Let's handle the potential overlap in C macros instead and get rid of that option. Currently, it was only used by most FSP1.0 boards, and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?). Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/bayleybay_fsp')
-rw-r--r--src/mainboard/intel/bayleybay_fsp/Kconfig4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig
index e8318cb0f2..7f74342427 100644
--- a/src/mainboard/intel/bayleybay_fsp/Kconfig
+++ b/src/mainboard/intel/bayleybay_fsp/Kconfig
@@ -38,10 +38,6 @@ config MAX_CPUS
int
default 16
-config CACHE_ROM_SIZE_OVERRIDE
- hex
- default 0x800000
-
config FSP_FILE
string
default "../intel/fsp/baytrail/BAYTRAIL_FSP_ECC.fd" if BOARD_INTEL_BAKERSPORT_FSP