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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-11-16 09:11:41 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-17 18:45:37 +0000 |
| commit | 05d7d82d37ae04ec4cf3579eb1c0f7bf0c0b7aa2 (patch) | |
| tree | d5af82e40f3b8b6617de0972df490abe27588ac4 /src/mainboard/intel/d945gclf | |
| parent | e7087a19bc158e1bbbe6b2bfaef53e38a644f99c (diff) | |
| download | coreboot-05d7d82d37ae04ec4cf3579eb1c0f7bf0c0b7aa2.tar.xz | |
mb/{i945,ich7}: Remove redundant write on V0CTL
RCBA32(V0CTL)= 0x80000001 already done inhere i945/early_init.c
Change-Id: Ia775f4e6158a217b48629d289845537e7ccf5e79
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/intel/d945gclf')
| -rw-r--r-- | src/mainboard/intel/d945gclf/early_init.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mainboard/intel/d945gclf/early_init.c b/src/mainboard/intel/d945gclf/early_init.c index c8dd3619c8..b4818e49ca 100644 --- a/src/mainboard/intel/d945gclf/early_init.c +++ b/src/mainboard/intel/d945gclf/early_init.c @@ -23,9 +23,6 @@ void mainboard_late_rcba_config(void) { - /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - /* dev irq route register */ RCBA16(D31IR) = 0x0132; RCBA16(D30IR) = 0x0146; |