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| author | Arthur Heymans <arthur@aheymans.xyz> | 2016-10-03 17:16:48 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2016-12-11 14:17:06 +0100 |
| commit | 885c289bba6554545ae21896a318f71e4ccb16a8 (patch) | |
| tree | 5be0a90c4d425bc950454c079ae0bbf311daf328 /src/mainboard/intel/d945gclf | |
| parent | 43e9c93eba3767f990aba518ef3e38c7a8892212 (diff) | |
| download | coreboot-885c289bba6554545ae21896a318f71e4ccb16a8.tar.xz | |
nb/intel/i945: Make pci_mmio_size a devicetree parameter
Instead of hardcoding pci_mmio_size in the raminit code,
this makes it a parameter in the devicetree.
A safe minimum of 768M is also defined since using anything
less causes problems (if 4G of ram is used).
Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16856
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/intel/d945gclf')
| -rw-r--r-- | src/mainboard/intel/d945gclf/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index aa8c441664..e8c2792420 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -21,6 +21,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on subsystemid 0x8086 0x464c inherit device pci 00.0 on end # host bridge |