summaryrefslogtreecommitdiff
path: root/src/mainboard/intel/leafhill/dsdt.asl
diff options
context:
space:
mode:
authorBrenton Dong <brenton.m.dong@intel.com>2017-01-04 16:39:43 -0700
committerMartin Roth <martinroth@google.com>2017-01-24 18:12:47 +0100
commitdcc0aa84fa20eaf8feefb21d1662d4716c64ad98 (patch)
tree47c981a0978a89335dbaaeab752046c91db6e7b1 /src/mainboard/intel/leafhill/dsdt.asl
parentd37fa8d84dc368aa02fa28134f2b7a38d2e3cdf9 (diff)
downloadcoreboot-dcc0aa84fa20eaf8feefb21d1662d4716c64ad98.tar.xz
mainboard/intel/leafhill: initial leafhill board changes
This commit makes the initial changes to support the Intel Leaf Hill CRB with Apollo Lake silicon. Memory parameters and some GPIOs are set. The google/reef directory is used as a template, and the same IFWI stitching process as reef is used to generate a bootable image. Apollo Lake silicon requires a boot media region called IFWI which includes assets such as CSE firmware, PMC microcode, CPU microcode, and boot firmware. Change-Id: Id92f0458548e3054d86f5faa8152d58d902f4418 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/18039 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/intel/leafhill/dsdt.asl')
-rw-r--r--src/mainboard/intel/leafhill/dsdt.asl26
1 files changed, 0 insertions, 26 deletions
diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl
index dc63436555..004523a0ff 100644
--- a/src/mainboard/intel/leafhill/dsdt.asl
+++ b/src/mainboard/intel/leafhill/dsdt.asl
@@ -13,9 +13,6 @@
* GNU General Public License for more details.
*/
-#include <variant/ec.h>
-#include <variant/gpio.h>
-
DefinitionBlock(
"dsdt.aml",
"DSDT",
@@ -40,29 +37,6 @@ DefinitionBlock(
}
}
- /* Chrome OS specific */
- #include <vendorcode/google/chromeos/acpi/chromeos.asl>
-
/* Chipset specific sleep states */
#include <soc/intel/apollolake/acpi/sleepstates.asl>
-
- /* Chrome OS Embedded Controller */
- Scope (\_SB.PCI0.LPCB)
- {
- /* ACPI code for EC SuperIO functions */
- #include <ec/google/chromeec/acpi/superio.asl>
- /* ACPI code for EC functions */
- #include <ec/google/chromeec/acpi/ec.asl>
- }
-
- /* Dynamic Platform Thermal Framework */
- Scope (\_SB)
- {
- /* Per board variant specific definitions. */
- #include <variant/acpi/dptf.asl>
- /* Include soc specific DPTF changes */
- #include <soc/intel/apollolake/acpi/dptf.asl>
- /* Include common dptf ASL files */
- #include <soc/intel/common/acpi/dptf/dptf.asl>
- }
}