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| author | Martin Roth <martin.roth@se-eng.com> | 2014-11-16 20:28:57 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-12-05 16:23:08 +0100 |
| commit | 30eda3edd72f70b3ff7ef46f5cb6e0e346683062 (patch) | |
| tree | fe77ef3ed78f6dec5ebc512ccc268a7c61fd30f3 /src/mainboard/intel/minnowmax/devicetree.cb | |
| parent | bdfe98f92fc1e9a69aa30ba87bb679dc28e9727c (diff) | |
| download | coreboot-30eda3edd72f70b3ff7ef46f5cb6e0e346683062.tar.xz | |
fsp_baytrail: remove register option for TSEG size
Set the UPD entry based on the Kconfig value instead of having two
separate places that the value needs to be set.
Change-Id: I3d32111b59152d0a8fc49e15320c7b5a140228a6
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7490
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Diffstat (limited to 'src/mainboard/intel/minnowmax/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/minnowmax/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index ae11d6a020..72849d6dfd 100644 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -28,7 +28,6 @@ chip soc/intel/fsp_baytrail register "PcdSataMode" = "SATA_MODE_AHCI" register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" - register "PcdMrcInitTsegSize" = "TSEG_SIZE_8_MB" register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" |