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authorArthur Heymans <arthur@aheymans.xyz>2019-05-12 13:44:22 +0200
committerNico Huber <nico.h@gmx.de>2019-05-14 23:22:02 +0000
commitcadc70f7974db25144381b3ea26d4b660233f4dd (patch)
treede9e0677c328fe3d90389298c00f8831d0a6984d /src/mainboard/intel/wtm2
parent57459dbeacb4759c3352206464b6c19b7add00d5 (diff)
downloadcoreboot-cadc70f7974db25144381b3ea26d4b660233f4dd.tar.xz
soc/intel/broadwell: Move GPIO init to a common place
This also links the gpio configuration instead of including it as a header. Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/intel/wtm2')
-rw-r--r--src/mainboard/intel/wtm2/Makefile.inc2
-rw-r--r--src/mainboard/intel/wtm2/gpio.c (renamed from src/mainboard/intel/wtm2/gpio.h)7
-rw-r--r--src/mainboard/intel/wtm2/romstage.c4
3 files changed, 3 insertions, 10 deletions
diff --git a/src/mainboard/intel/wtm2/Makefile.inc b/src/mainboard/intel/wtm2/Makefile.inc
index 16137462c9..4c944f2773 100644
--- a/src/mainboard/intel/wtm2/Makefile.inc
+++ b/src/mainboard/intel/wtm2/Makefile.inc
@@ -13,6 +13,8 @@
## GNU General Public License for more details.
##
+romstage-y += gpio.c
+
romstage-y += chromeos.c
ramstage-y += chromeos.c
diff --git a/src/mainboard/intel/wtm2/gpio.h b/src/mainboard/intel/wtm2/gpio.c
index 9e6f2e6445..c81ad10081 100644
--- a/src/mainboard/intel/wtm2/gpio.h
+++ b/src/mainboard/intel/wtm2/gpio.c
@@ -13,12 +13,9 @@
* GNU General Public License for more details.
*/
-#ifndef INTEL_WTM2_GPIO_H
-#define INTEL_WTM2_GPIO_H
-
#include <soc/gpio.h>
-static const struct gpio_config mainboard_gpio_config[] = {
+const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */
PCH_GPIO_NATIVE, /* 1: LPSS_UART1_TXD */
PCH_GPIO_NATIVE, /* 2: LPSS_UART1_RTS_N_R */
@@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_NATIVE, /* 94: LPSS_UART0_CTS_N */
PCH_GPIO_END
};
-
-#endif
diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c
index 3c9bb36363..de4237d222 100644
--- a/src/mainboard/intel/wtm2/romstage.c
+++ b/src/mainboard/intel/wtm2/romstage.c
@@ -21,7 +21,6 @@
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/romstage.h>
-#include "gpio.h"
void mainboard_romstage_entry(struct romstage_params *rp)
{
@@ -29,9 +28,6 @@ void mainboard_romstage_entry(struct romstage_params *rp)
post_code(0x32);
- /* Initialize GPIOs */
- init_gpios(mainboard_gpio_config);
-
/* Fill out PEI DATA */
memset(&pei_data, 0, sizeof(pei_data));
mainboard_fill_pei_data(&pei_data);