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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-05-03 15:53:33 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-05-17 21:38:17 +0200 |
| commit | 4bab6e79b078c76d0a42883c4b4c9c68615d5a1e (patch) | |
| tree | 2c7dda58587f464fa1baee712c95bb48c924ff76 /src/mainboard/iwave/iWRainbowG6/romstage.c | |
| parent | 083da160af4a0e3a76506af59477f105d78b9683 (diff) | |
| download | coreboot-4bab6e79b078c76d0a42883c4b4c9c68615d5a1e.tar.xz | |
intel/sch: Merge northbridge and southbridge in src/soc
Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14599
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Diffstat (limited to 'src/mainboard/iwave/iWRainbowG6/romstage.c')
| -rw-r--r-- | src/mainboard/iwave/iWRainbowG6/romstage.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index c567a4acf3..37b442c0be 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -24,7 +24,7 @@ #include <console/console.h> #if 0 #include "ram/ramtest.c" -#include "southbridge/intel/sch/early_smbus.c" +#include "soc/intel/sch/early_smbus.c" #endif #define RFID_TEST 0 @@ -268,9 +268,9 @@ int selectcard(void) } #endif -#include "northbridge/intel/sch/early_init.c" -#include <northbridge/intel/sch/raminit.h> -#include "northbridge/intel/sch/raminit.c" +#include "soc/intel/sch/early_init.c" +#include <soc/intel/sch/raminit.h> +#include "soc/intel/sch/raminit.c" static void sch_enable_lpc(void) { |