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authorSven Schnelle <svens@stackframe.org>2011-04-20 08:58:38 +0000
committerSven Schnelle <svens@stackframe.org>2011-04-20 08:58:38 +0000
commit81725b2effe9269e5079c6043077ba516e72aa82 (patch)
tree36d93d3eaa95598bef4c64e6595aa454993cfa5e /src/mainboard/nokia/ip530
parent5c72a8752bb5ce1c3b1bfb77c08039c71c2113ef (diff)
downloadcoreboot-81725b2effe9269e5079c6043077ba516e72aa82.tar.xz
pci1x2x: remove latency/bridge control/cacheline size settings
Those settings should be handled by the generic PCI/Cardbus code, and not by the driver itself. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/nokia/ip530')
-rw-r--r--src/mainboard/nokia/ip530/devicetree.cb2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/nokia/ip530/devicetree.cb b/src/mainboard/nokia/ip530/devicetree.cb
index a132604472..f89d1cd9fe 100644
--- a/src/mainboard/nokia/ip530/devicetree.cb
+++ b/src/mainboard/nokia/ip530/devicetree.cb
@@ -33,8 +33,6 @@ chip northbridge/intel/i440bx # Northbridge
device pci 00.0 on
subsystemid 0x13b8 0x0000
end
- register "cltr" = "0x40"
- register "bcr" = "0x7c0"
register "scr" = "0x08449060"
register "mrr" = "0x00007522"
end