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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2021-04-30 12:43:41 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-07 13:19:50 +0000 |
| commit | 1749f272758b59f1717d34a5f1c67710f29cfbb5 (patch) | |
| tree | f68ce5bdda6255e03b7ec4a18068d4bd059fb9c9 /src/mainboard/pcengines | |
| parent | 8e23270405b4ecd27abb02af9cc8a985aa01edcf (diff) | |
| download | coreboot-1749f272758b59f1717d34a5f1c67710f29cfbb5.tar.xz | |
mb/pcengines/apu1: Disable memory bank interleaving
Bank interleaving does not work on this platform, disable it.
AmdInitPost returns success thanks to this setting.
TEST=boot apu1 and see AGESA_SUCCESS after AmdInitPost
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id555b458c61df9a27a93f44f600d1718867106ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/pcengines')
| -rw-r--r-- | src/mainboard/pcengines/apu1/OemCustomize.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c index d6edf03e8b..254947cf8c 100644 --- a/src/mainboard/pcengines/apu1/OemCustomize.c +++ b/src/mainboard/pcengines/apu1/OemCustomize.c @@ -101,4 +101,6 @@ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) { InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; + /* Bank interleaving is not supported on this platform */ + InitPost->MemConfig.EnableBankIntlv = FALSE; } |