diff options
| author | Krystian Hebel <krystian.hebel@3mdeb.com> | 2018-12-21 18:19:14 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-12-28 22:39:40 +0000 |
| commit | fba03208428fd11acc69e0b3b00bf358cc83f7de (patch) | |
| tree | ade76a3921133b3283f1c4be7c71c0ca3d268788 /src/mainboard/pcengines | |
| parent | 69b6c56909653f5fd438fbd5d5ffb44d6de7a974 (diff) | |
| download | coreboot-fba03208428fd11acc69e0b3b00bf358cc83f7de.tar.xz | |
mb/pcengines/apu2/romstage.c: disable SVI2 wait completion
On some platforms SVI command completion is not reported by
voltage regulator. Because of that CPU got stuck in invalid
P-State, which resulted in lower frequency and inability to
reboot platform without performing cold reset.
Change-Id: I260c997f3a0f4547041785a3b9de78e34d22812a
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/30367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/pcengines')
| -rw-r--r-- | src/mainboard/pcengines/apu2/romstage.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index a4bd816506..a1720d2ab4 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -105,6 +105,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); + /* Disable SVI2 controller to wait for command completion */ + val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); + if (val & (1 << 30)) { + printk(BIOS_DEBUG, "SVI2 Wait completion disabled\n"); + } else { + printk(BIOS_DEBUG, "Disabling SVI2 Wait completion\n"); + val |= (1 << 30); + pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val); + } + timestamp_add_now(TS_BEFORE_INITRAM); post_code(0x40); |