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| author | Matt DeVillier <matt.devillier@puri.sm> | 2020-11-03 13:27:43 -0600 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-04 20:29:21 +0000 |
| commit | 0d29bb72a18a5e4866c4494bf509f1e7dd954003 (patch) | |
| tree | e1a72ae7aa742d2cb76abcf3e4bfdb411294979a /src/mainboard/purism/librem_cnl | |
| parent | b808e7678d79994dbc5ed4cfaff20959222e5c2e (diff) | |
| download | coreboot-0d29bb72a18a5e4866c4494bf509f1e7dd954003.tar.xz | |
mb/purism_librem_mini: Add child device, slot descriptions to PCIe RPs
Change-Id: Id306100fc691dcbde48b65092d0be9d7e73c0722
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47189
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/purism/librem_cnl')
| -rw-r--r-- | src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index c69f3f635e..9fde5e97da 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -204,22 +204,29 @@ chip soc/intel/cannonlake device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on # PCI Express Port 8 (WLAN) + device pci 1c.7 on # PCI Express Port 8 + chip drivers/wifi/generic + device pci 00.0 on end # x1 M.2/E 2230 (WLAN) + end register "PcieRpSlotImplemented[7]" = "1" register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" end device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 on # PCI Express Port 10 (LAN) + device pci 1d.1 on # PCI Express Port 10 + device pci 00.0 on end # x1 (LAN) register "PcieRpSlotImplemented[9]" = "1" register "PcieRpEnable[9]" = "1" end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on # PCI Express Port 13 (NVMe) + device pci 1d.4 on # PCI Express Port 13 + device pci 00.0 on end # x4 M.2/M 2280 (NVMe) register "PcieRpSlotImplemented[12]" = "1" register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 |