diff options
| author | Youness Alaoui <youness.alaoui@puri.sm> | 2017-06-15 16:50:47 -0400 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-22 01:58:01 +0000 |
| commit | 3d60718f8239174b0d968666f39a86849ceea7cf (patch) | |
| tree | 5990d52cbd1ee9d3474ceb48c78d3f2f1350e67f /src/mainboard/purism | |
| parent | c0a32cad28a5557fd34171bf1cedb63ca1f1ebe0 (diff) | |
| download | coreboot-3d60718f8239174b0d968666f39a86849ceea7cf.tar.xz | |
purism/librem13v2: Change DRAM Rcomp/DQS values
The RComp values have been updated to match what is shown in the schematics.
Extracting the Memory configuration blob from the original BIOS (A blob
which contains the correct binary sequence matching the RComp values appears
in object with GUID 2D27C618-7DCD-41F5-BB10-21166BE7E143), I could find
and confirm the DQ and DQS mapping.
Small code cleaning in romstage.c with no effect.
Change-Id: I35c734269b365fd759e9bd56224a80a8a8df5a57
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/22041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/purism')
| -rw-r--r-- | src/mainboard/purism/librem13v2/pei_data.c | 6 | ||||
| -rw-r--r-- | src/mainboard/purism/librem13v2/romstage.c | 5 |
2 files changed, 6 insertions, 5 deletions
diff --git a/src/mainboard/purism/librem13v2/pei_data.c b/src/mainboard/purism/librem13v2/pei_data.c index 84f38d9719..730b7307be 100644 --- a/src/mainboard/purism/librem13v2/pei_data.c +++ b/src/mainboard/purism/librem13v2/pei_data.c @@ -29,14 +29,14 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { - { 0, 3, 1, 2, 4, 5, 6, 7 }, + { 0, 1, 3, 2, 4, 5, 6, 7 }, { 1, 0, 4, 5, 2, 3, 6, 7 } }; /* Rcomp resistor */ - const u16 RcompResistor[3] = { 200, 81, 162 }; + const u16 RcompResistor[3] = { 121, 81, 100 }; /* Rcomp target */ - const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); diff --git a/src/mainboard/purism/librem13v2/romstage.c b/src/mainboard/purism/librem13v2/romstage.c index c8c3cd9510..fc940e1a67 100644 --- a/src/mainboard/purism/librem13v2/romstage.c +++ b/src/mainboard/purism/librem13v2/romstage.c @@ -38,11 +38,11 @@ void mainboard_memory_init_params(struct romstage_params *params, .addr_map = { 0x50 }, }; - memory_params->DqPinsInterleaved = 1; get_spd_smbus(&blk); dump_spd_info(&blk); - memory_params->MemorySpdDataLen = blk.len; assert(blk.spd_array[0][0] != 0); + + memory_params->MemorySpdDataLen = blk.len; memory_params->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; memory_params->MemorySpdPtr01 = 0; memory_params->MemorySpdPtr10 = 0; @@ -60,5 +60,6 @@ void mainboard_memory_init_params(struct romstage_params *params, sizeof(params->pei_data->RcompResistor)); memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget, sizeof(params->pei_data->RcompTarget)); + memory_params->DqPinsInterleaved = TRUE; } |