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authorMichael Niewöhner <foss@mniewoehner.de>2020-10-15 00:36:29 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-10-26 06:51:42 +0000
commita64b4f454894988a9c043d53d00b493852f261a3 (patch)
tree44aacf270999724b4461edb3b4c35959482b4330 /src/mainboard/purism
parentd5a45470c816bc8a8bdc43951c9e4c4a592b55d3 (diff)
downloadcoreboot-a64b4f454894988a9c043d53d00b493852f261a3.tar.xz
mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`
The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src/mainboard/purism')
-rw-r--r--src/mainboard/purism/librem_skl/devicetree.cb3
-rw-r--r--src/mainboard/purism/librem_whl/devicetree.cb3
2 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index 23c57120f1..2c73280148 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -37,9 +37,6 @@ chip soc/intel/skylake
register "gen1_dec" = "0x00000381"
register "gen2_dec" = "0x000c0081"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
# Disable DPTF
register "dptf_enable" = "0"
diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_whl/devicetree.cb
index 497a4cca4d..205033230b 100644
--- a/src/mainboard/purism/librem_whl/devicetree.cb
+++ b/src/mainboard/purism/librem_whl/devicetree.cb
@@ -24,9 +24,6 @@ chip soc/intel/cannonlake
.tdp_pl2_override = 28,
}"
- # Enable "Intel Speed Shift Technology"
- register "speed_shift_enable" = "1"
-
# Enable Enhanced Intel SpeedStep
register "eist_enable" = "1"