diff options
| author | Matt DeVillier <matt.devillier@puri.sm> | 2020-11-04 15:04:06 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-09 07:47:36 +0000 |
| commit | e9523926152490d3f1c70ff8773b87ee54084e55 (patch) | |
| tree | bf35436979110208965bf36d5ad8b9369bd60ba5 /src/mainboard/purism | |
| parent | 4d4256e499e850a724d228d2e676c0f32af67093 (diff) | |
| download | coreboot-e9523926152490d3f1c70ff8773b87ee54084e55.tar.xz | |
mb/purism/librem_mini: Fix PCIe clock source mapping in devicetree
Correct PCIe clock source mapping in devicetree now that the GPIO
config has been fixed. Move ClkSrcUsage/ClkSrcClkReq registers
under their associated PCIe root ports.
Change-Id: Ibdaba51d971a39a6da6df82652b7420d7324dee5
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/mainboard/purism')
| -rw-r--r-- | src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb | 22 |
1 files changed, 6 insertions, 16 deletions
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 918fa0ef0e..becb9468c7 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -19,22 +19,6 @@ chip soc/intel/cannonlake # FSP Silicon (soc/intel/cannonlake/fsp_params.c) - # All SRCCLKREQ pins mapped directly - register "PcieClkSrcClkReq[0]" = "0" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieClkSrcClkReq[5]" = "5" - - # Set all SRCCLKREQ pins as free-use - register "PcieClkSrcUsage[0]" = "0x80" - register "PcieClkSrcUsage[1]" = "0x80" - register "PcieClkSrcUsage[2]" = "0x80" - register "PcieClkSrcUsage[3]" = "0x80" - register "PcieClkSrcUsage[4]" = "0x80" - register "PcieClkSrcUsage[5]" = "0x80" - # Misc register "AcousticNoiseMitigation" = "1" @@ -211,6 +195,8 @@ chip soc/intel/cannonlake register "PcieRpSlotImplemented[7]" = "1" register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" + # ClkSrcUsage must be set to free-run since SRCCLKREQ2 is NC + register "PcieClkSrcUsage[2]" = "0x80" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" end device pci 1d.0 off end # PCI Express Port 9 @@ -218,6 +204,8 @@ chip soc/intel/cannonlake device pci 00.0 on end # x1 (LAN) register "PcieRpSlotImplemented[9]" = "1" register "PcieRpEnable[9]" = "1" + register "PcieClkSrcUsage[3]" = "9" + register "PcieClkSrcClkReq[3]" = "3" end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 @@ -226,6 +214,8 @@ chip soc/intel/cannonlake register "PcieRpSlotImplemented[12]" = "1" register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[1]" = "12" + register "PcieClkSrcClkReq[1]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device pci 1d.5 off end # PCI Express Port 14 |