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| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-04-10 22:51:15 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-04-12 16:52:19 +0000 |
| commit | c5f1dc96bf0b18245d7986463ae56958c44d24f2 (patch) | |
| tree | ed6b20f2b323d3ff835812aa98bf9450b177c4ec /src/mainboard/razer | |
| parent | c1ec940eba11d279912b24377a7cf8ab4b264aaa (diff) | |
| download | coreboot-c5f1dc96bf0b18245d7986463ae56958c44d24f2.tar.xz | |
mb/*: drop LPC generic range for port 80
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have
to be set up as generic range. Drop the entries from the devicetrees.
Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/razer')
| -rw-r--r-- | src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index a358fb8374..a4951fe9de 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -15,9 +15,8 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x000c0081" - register "gen2_dec" = "0x000c0681" - register "gen3_dec" = "0x000c1641" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" # Disable DPTF register "dptf_enable" = "0" |