summaryrefslogtreecommitdiff
path: root/src/mainboard/sapphire/pureplatinumh61
diff options
context:
space:
mode:
authorPatrick Rudolph <patrick.rudolph@9elements.com>2019-07-15 18:04:23 +0200
committerPatrick Rudolph <siro@das-labor.org>2019-07-19 15:06:23 +0000
commitb30a47b841f1c7d55d9cf207e1cc89f1b7f7fa51 (patch)
tree26768bd5cafaf5615c4e2e80cee0835308d882d2 /src/mainboard/sapphire/pureplatinumh61
parentfa0ef81d155a913b857055c6ce81e628ff866742 (diff)
downloadcoreboot-b30a47b841f1c7d55d9cf207e1cc89f1b7f7fa51.tar.xz
sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supported
The processor P_BLK doesn't support throttling. This behaviour could be emulated with SMM, but instead just update the FADT to indicate no support for legacy I/O based throttling using P_CNT. We have _PTC defined in SSDT, which should be used in favour of P_CNT by ACPI aware OS, so this change has no effect on modern OS. Drop all occurences of p_cnt_throttling_supported and update autoport to not generate it any more. Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/sapphire/pureplatinumh61')
-rw-r--r--src/mainboard/sapphire/pureplatinumh61/devicetree.cb1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
index 95c59dfca3..aff01302b2 100644
--- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
+++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb
@@ -50,7 +50,6 @@ chip northbridge/intel/sandybridge
register "gen2_dec" = "0x000c0a01"
register "gen3_dec" = "0x00000000"
register "gen4_dec" = "0x00000000"
- register "p_cnt_throttling_supported" = "0"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"