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authorRudolf Marek <r.marek@assembler.cz>2010-09-22 22:46:47 +0000
committerRudolf Marek <r.marek@assembler.cz>2010-09-22 22:46:47 +0000
commit7df50a8b0ead14610134e57b05a81340febd8db8 (patch)
tree65d43878463989a88c8383543f387679c8782c06 /src/mainboard
parent138cdbb17b9ae8543a65a6b61ab6daac5c6ef7f7 (diff)
downloadcoreboot-7df50a8b0ead14610134e57b05a81340febd8db8.tar.xz
Here is a proposed way how to handle the SATA PHY settings on SB700. It
consits of weak function which always exists (with defaults) and a possibility to override this with normal function in main.c. This is the other way of doing that and not using the devictree.cb. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/asrock/939a785gmh/mainboard.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c
index 9cebdc2000..09ace66fca 100644
--- a/src/mainboard/asrock/939a785gmh/mainboard.c
+++ b/src/mainboard/asrock/939a785gmh/mainboard.c
@@ -147,3 +147,25 @@ struct chip_operations mainboard_ops = {
CHIP_NAME("Asrock 939A785GMH/128M Mainboard")
.enable_dev = mb_enable,
};
+
+/* override the default SATA PHY setup */
+void sb700_setup_sata_phys(struct device *dev) {
+ /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
+ pci_write_config16(dev, 0x86, 0x2c00);
+
+ /* RPR7.6.2 SATA GENI PHY ports setting */
+ pci_write_config32(dev, 0x88, 0x01B48016);
+ pci_write_config32(dev, 0x8c, 0x01B48016);
+ pci_write_config32(dev, 0x90, 0x01B48016);
+ pci_write_config32(dev, 0x94, 0x01B48016);
+ pci_write_config32(dev, 0x98, 0x01B48016);
+ pci_write_config32(dev, 0x9C, 0x01B48016);
+
+ /* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
+ pci_write_config16(dev, 0xA0, 0xA07A);
+ pci_write_config16(dev, 0xA2, 0xA07A);
+ pci_write_config16(dev, 0xA4, 0xA07A);
+ pci_write_config16(dev, 0xA6, 0xA07A);
+ pci_write_config16(dev, 0xA8, 0xA07A);
+ pci_write_config16(dev, 0xAA, 0xA0FF);
+}