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authorRoy Mingi Park <roy.mingi.park@intel.com>2019-06-03 16:11:25 -0700
committerDuncan Laurie <dlaurie@chromium.org>2019-06-04 16:49:46 +0000
commit06cfb21e243ec74660e4886cef2f2e9c6c755d9e (patch)
tree19ec89696683d0864e5df4952a57e22b9f705e4c /src/mainboard
parent13539d2f9d671099764f12e45b8e6d4e41c8e4af (diff)
downloadcoreboot-06cfb21e243ec74660e4886cef2f2e9c6c755d9e.tar.xz
mb/google/sarien: Fix SSD's power off sequence before going to S5
BUG=b:133389422 TEST=check SSD's power off sequence to meet PCIE requirement. SSD's reset should be cleared before clearing SSD's power EN Pin. Change-Id: Ia106b805deafb8a442b56bcce91b51135cb32988 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33182 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl3
-rw-r--r--src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl3
2 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
index 6eba2bcb21..4b05ba8e90 100644
--- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
@@ -40,8 +40,9 @@ Method (MPTS, 1)
/* Clear SSD EN adn RST pin to avoid leakage */
If (Arg0 == 5) {
- \_SB.PCI0.CTXS (SSD_EN)
\_SB.PCI0.CTXS (SSD_RST)
+ Sleep(1)
+ \_SB.PCI0.CTXS (SSD_EN)
}
}
diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
index 6eba2bcb21..4b05ba8e90 100644
--- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
@@ -40,8 +40,9 @@ Method (MPTS, 1)
/* Clear SSD EN adn RST pin to avoid leakage */
If (Arg0 == 5) {
- \_SB.PCI0.CTXS (SSD_EN)
\_SB.PCI0.CTXS (SSD_RST)
+ Sleep(1)
+ \_SB.PCI0.CTXS (SSD_EN)
}
}