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authorScott Duplichan <scott@notabs.org>2011-05-20 17:50:14 +0000
committerScott Duplichan <scott@notabs.org>2011-05-20 17:50:14 +0000
commitfb93178f13c49c786ba142b119de9245eaf5b52b (patch)
tree18f63d45eb9db4d2ad5582081c25ecb353fbf7e9 /src/mainboard
parent20aad25e6e8275815cfdbf4fbb07f9317e3c4812 (diff)
downloadcoreboot-fb93178f13c49c786ba142b119de9245eaf5b52b.tar.xz
Correct amd persimmon romstage code for early SPI prefetch enable.
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Scott Duplichan <scott@notabs.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/amd/persimmon/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c
index 1bcb0d1407..3f2aa10329 100644
--- a/src/mainboard/amd/persimmon/romstage.c
+++ b/src/mainboard/amd/persimmon/romstage.c
@@ -74,7 +74,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (boot_cpu())
{
__outdword (0xcf8, 0x8000a3b8);
- __outdword (0xcfc, __indword (0xcfc) | 0 << 24);
+ __outdword (0xcfc, __indword (0xcfc) | 1 << 24);
}
// early enable of SPI 33 MHz fast mode read