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author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-11-24 14:11:47 -0600 |
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committer | Martin Roth <martinroth@google.com> | 2016-01-24 23:20:02 +0100 |
commit | 19ce16ae69f31ef37c5edcbc3621a8060176b7e9 (patch) | |
tree | a2f93ed4236e62fb56b7baa4d65f31ff2cc01b57 /src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | |
parent | a39e6d1cf90a2be7a5311625b5d6be85921e8977 (diff) | |
download | coreboot-19ce16ae69f31ef37c5edcbc3621a8060176b7e9.tar.xz |
northbridge/amd/amdfam10: Update DRAM speed limits for C32 sockets
The existing code applied G34-specific speed limits to all socket
types. Update G34 and C32 specific speed limits to be in line with
BKDG recommendations.
Change-Id: I958ad333c47948ae741a56de5866af3e636fd24d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13140
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.c')
0 files changed, 0 insertions, 0 deletions