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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-04-21 01:18:36 -0500 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-04-22 17:32:20 +0200 |
| commit | 8b9c807d724a4d211306bc84cff0b1290fcd1891 (patch) | |
| tree | 1ace4ebe7d44e8d8e99ef8fa29f76294b146649f /src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | |
| parent | 5a359365b9ba0e4868f3d15f25d60c6cb321cada (diff) | |
| download | coreboot-8b9c807d724a4d211306bc84cff0b1290fcd1891.tar.xz | |
Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training"
After substantial testing it has been determined that it is neither
required nor safe to disable the DRAM MCA during initial startup.
This (mostly) reverts commit c094d9961144871c472698c41ce634e58abb6a32.
The minor debugging enhancements from that commit were left in place.
Tested-On: ASUS KGPE-D16
Config-CPU: 1x Opteron 6262HE
Config-RAM: 4x Crucial 36KSF1G72PZ-1G6M1
Config-RAM: 1x Kingston 9965516-483.A00LF
Change-Id: I58fcc296b8c45ecaedf540951c365e4ce52baaf5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14446
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 3582efa451..284e8906cc 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -8049,19 +8049,6 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "mct_SetDramConfigHi_D: DramConfigHi: %08x\n", DramConfigHi); - /* Prevent lockups on parity errors during initial DCT startup */ - if (!pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - pDCTstat->sync_flood_on_dram_err = (dword >> 30) & 0x1; - pDCTstat->sync_flood_on_any_uc_err = (dword >> 21) & 0x1; - pDCTstat->sync_flood_on_uc_dram_ecc_err = (dword >> 2) & 0x1; - dword &= ~(0x1 << 30); - dword &= ~(0x1 << 21); - dword &= ~(0x1 << 2); - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - pDCTstat->mca_config_backed_up = 1; - } - /* Program the DRAM Configuration High register */ Set_NB32_DCT(dev, dct, 0x94, DramConfigHi); |