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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-06-09 11:59:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:32:34 +0000 |
| commit | b0f1988f893bf5f581917816b11e810309955143 (patch) | |
| tree | c4bcf6f1d9384b99cfcbfab4426de9f9f106e720 /src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | |
| parent | 68c851bcd702e7816cdb6e504f7386ec404ecf13 (diff) | |
| download | coreboot-b0f1988f893bf5f581917816b11e810309955143.tar.xz | |
src: Get rid of unneeded whitespace
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mct_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index da803ff627..7421c18a69 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2346,7 +2346,7 @@ void set_2t_configuration(struct MCTStatStruc *pMCTstat, enable_slow_access_mode = 1; } - reg = 0x94; /* DRAM Configuration High */ + reg = 0x94; /* DRAM Configuration High */ dword = Get_NB32_DCT(dev, dct, reg); if (enable_slow_access_mode) dword |= (0x1 << 20); /* Set 2T CMD mode */ @@ -2539,7 +2539,7 @@ static void set_cc6_save_enable(struct MCTStatStruc *pMCTstat, uint32_t dword; dword = Get_NB32(pDCTstat->dev_dct, 0x118); - dword &= ~(0x1 << 18); /* CC6SaveEn = enable */ + dword &= ~(0x1 << 18); /* CC6SaveEn = enable */ dword |= (enable & 0x1) << 18; Set_NB32(pDCTstat->dev_dct, 0x118, dword); } @@ -7908,10 +7908,11 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat, * Solution: From the bug report: * 1. A software-initiated frequency change should be wrapped into the * following sequence : - * - a) Disable Compensation (F2[1, 0]9C_x08[30]) - * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines - * c) Do frequency change - * d) Enable Compensation (F2[1, 0]9C_x08[30]) + * a) Disable Compensation (F2[1, 0]9C_x08[30]) + * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in + * all the compensation engines + * c) Do frequency change + * d) Enable Compensation (F2[1, 0]9C_x08[30]) * 2. A software-initiated Disable Compensation should always be * followed by step b) of the above steps. * Silicon Status: Fixed In Rev B0 |