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| author | Martin Roth <martinroth@google.com> | 2016-11-18 09:29:03 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-21 23:43:54 +0100 |
| commit | 128c104c4d3b91d3371b03840af460d776af819d (patch) | |
| tree | bb0621ae2c90b512948ba9fee350cf42a49f4db3 /src/northbridge/intel/gm45/bootblock.c | |
| parent | c6ec8dd1cb2303f7f7a71f0f494a6fc30b93dff4 (diff) | |
| download | coreboot-128c104c4d3b91d3371b03840af460d776af819d.tar.xz | |
nb/intel: Fix some spelling mistakes in comments and strings
Change-Id: I4a8297397d878e38516c8df19dd311c7ef19ec06
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17478
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/gm45/bootblock.c')
| -rw-r--r-- | src/northbridge/intel/gm45/bootblock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index fb40b9446a..10c64e9021 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -15,7 +15,7 @@ static void bootblock_northbridge_init(void) * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. |