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authorStefan Reinauer <reinauer@chromium.org>2013-05-20 16:23:40 -0700
committerRonald G. Minnich <rminnich@gmail.com>2013-06-21 19:36:55 +0200
commitd358a506c4230950e34d783bd0187cd200d60691 (patch)
tree089c30c5d04c0ebec8e9aa5b92bc2de92f56b109 /src/northbridge/intel/haswell
parent8a0a8488fec6ee3b94e9f1416cc839a20e47573e (diff)
downloadcoreboot-d358a506c4230950e34d783bd0187cd200d60691.tar.xz
Add support to enable/disable builtin GbE
In case we are going to use this in future designs. BUG=none TEST=none BRANCH=none Change-Id: I750addf10e4fe6f8240f8c8262253f8af7027e29 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/55844 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3515 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/haswell')
-rw-r--r--src/northbridge/intel/haswell/pei_data.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h
index 280c73b75a..7c10e41844 100644
--- a/src/northbridge/intel/haswell/pei_data.h
+++ b/src/northbridge/intel/haswell/pei_data.h
@@ -31,7 +31,7 @@
#define PEI_DATA_H
typedef void (*tx_byte_func)(unsigned char byte);
-#define PEI_VERSION 10
+#define PEI_VERSION 11
struct pei_data
{
@@ -53,6 +53,7 @@ struct pei_data
uint8_t spd_addresses[4];
int boot_mode;
int ec_present;
+ int gbe_enable;
// 0 = leave channel enabled
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel