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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-09 22:10:33 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-07 06:42:14 +0000 |
| commit | 4bdfebd4d88c1d84662cae3d11de1ee40f9e0017 (patch) | |
| tree | 561e703f590100dcdd93b3f9cb55825235636cc4 /src/northbridge/intel/pineview/pineview.h | |
| parent | e07df9d78351cda0818309fc7f3e78d8057d421e (diff) | |
| download | coreboot-4bdfebd4d88c1d84662cae3d11de1ee40f9e0017.tar.xz | |
nb/intel/pineview: Enable and allocate 8M for TSEG
TSEG can be used as a stage cache and SMM can be relocated here.
Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25593
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/pineview/pineview.h')
| -rw-r--r-- | src/northbridge/intel/pineview/pineview.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index a2cda84428..9873d4de81 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -62,7 +62,7 @@ #define REMAPBASE 0x98 #define REMAPLIMIT 0x9a #define SMRAM 0x9d /* System Management RAM Control */ -#define ESMRAM 0x9e /* Extended System Management RAM Control */ +#define ESMRAMC 0x9e /* Extended System Management RAM Control */ #define TOM 0xa0 #define TOUUD 0xa2 |