nb/intel/sandybridge: Tidy up code and comments

- Reformat some lines of code
- Move MCHBAR registers and documentation into a separate file
- Add a few missing macros
- Rename some registers
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)

With BUILD_TIMELESS=1, this commit does not change the result of:
- Asus P8Z77-V LX2 with native raminit.
- Asus P8Z77-M PRO with MRC raminit.

Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39599
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/src/northbridge/intel/sandybridge/raminit_native.h b/src/northbridge/intel/sandybridge/raminit_native.h
index ecf13cf1f8..60a5665ba9 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.h
+++ b/src/northbridge/intel/sandybridge/raminit_native.h
@@ -18,8 +18,8 @@
 #include "sandybridge.h"
 #include <device/dram/ddr3.h>
 
-/* The order is ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB.  */
+/* The order is: ch0dimmA, ch0dimmB, ch1dimmA, ch1dimmB */
 void read_spd(spd_raw_data *spd, u8 addr, bool id_only);
 void mainboard_get_spd(spd_raw_data *spd, bool id_only);
 
-#endif				/* RAMINIT_H */
+#endif /* RAMINIT_NATIVE_H */