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| author | Sebastian Andrzej Siewior <bigeasy@linutronix.de> | 2012-10-26 19:00:22 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-10-26 21:54:42 +0200 |
| commit | 66fa9e2865dc68fd3d89714138c8e0d27ff16819 (patch) | |
| tree | 424a8dce999a2a756313d0ef7bc1290319320d61 /src/northbridge/intel | |
| parent | cd02793dffe147030e78a9f609611f7615dda3a6 (diff) | |
| download | coreboot-66fa9e2865dc68fd3d89714138c8e0d27ff16819.tar.xz | |
northbridge/sch: don't overwrite hightables with GPU / TSEG memory
Without this, the hightables are placed just before the end of memory.
However we might have the GPU memory located at the exact same spot,
that is in the last 4 MiB. So without this patch, this area won't remain
marked as "CONFIGURATION TABLES" within coreboot's memory table but
becomes "RESERVED" because it is part of the PCI(2,0) device.
Change-Id: Ibd111c167c2f6ac03b0ba68581a74ecbd2c9c160
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-on: http://review.coreboot.org/1627
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/sch/northbridge.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 16ada2fa6c..fb3bff8492 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -188,7 +188,9 @@ static void pci_domain_set_resources(device_t dev) #if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables. */ - high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; + high_tables_base = tomk * 1024 - HIGH_MEMORY_SIZE; + high_tables_base -= uma_memory_size; + high_tables_base -= tseg_memory_base; high_tables_size = HIGH_MEMORY_SIZE; #endif } |