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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-04 01:07:24 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-12 11:14:23 +0000 |
| commit | 39a6093d7937dec85077f754fbcaa2e2be493eae (patch) | |
| tree | 6e76384b8788982afb6bec2267dffabd4548c2fc /src/northbridge | |
| parent | d37b7d89fd362242fd5da11303c7bb18bf78afcf (diff) | |
| download | coreboot-39a6093d7937dec85077f754fbcaa2e2be493eae.tar.xz | |
haswell: Automatically check if Intel GbE is to be enabled
If the Intel in-PCH GbE MAC is enabled in the devicetree, then tell MRC
to enable it as well. No one can ever forget to set this option anymore!
Change-Id: I946af36d16c94bb1a0f146604d0329fe6d6ce7e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43128
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 2961299e7d..7016fd9a7e 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -3,6 +3,7 @@ #include <arch/romstage.h> #include <console/console.h> #include <cf9_reset.h> +#include <device/device.h> #include <timestamp.h> #include <cpu/x86/lapic.h> #include <cbmem.h> @@ -37,6 +38,8 @@ static int make_channel_disabled_mask(const struct pei_data *pd, int ch) /* The romstage entry point for this platform is not mainboard-specific, hence the name */ void mainboard_romstage_entry(void) { + const struct device *gbe = pcidev_on_root(0x19, 0); + int wake_from_s3; struct pei_data pei_data = { @@ -53,6 +56,7 @@ void mainboard_romstage_entry(void) .temp_mmio_base = 0xfed08000, .system_type = get_pch_platform_type(), .tseg_size = CONFIG_SMM_TSEG_SIZE, + .gbe_enable = gbe && gbe->enabled, .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), .max_ddr3_freq = 1600, }; |