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authorKyösti Mälkki <kyosti.malkki@gmail.com>2012-07-03 11:36:44 +0300
committerMarc Jones <marc.jones@se-eng.com>2013-03-07 00:48:02 +0100
commit41dd3dbd5e5619b9957de6850541af7cfe21a1a8 (patch)
treef3dc45f0bb7a8847576c3e948da2c91f78286ae9 /src/northbridge
parent5a22b14d47955a2cce1d51d883a3c0ee4df39df0 (diff)
downloadcoreboot-41dd3dbd5e5619b9957de6850541af7cfe21a1a8.tar.xz
Intel e7505: provide get_top_of_ram
This is required to enable EARLY_CBMEM_INIT. Change-Id: I6d8caf382aa48eded81c1e94bbbcd3975ea88a1a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/2550 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/e7505/raminit.c6
-rw-r--r--src/northbridge/intel/e7505/raminit.h1
2 files changed, 7 insertions, 0 deletions
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 2f558f5231..9fba602833 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -1889,6 +1889,12 @@ void e7505_mch_init(const struct mem_controller *memctrl)
sdram_enable(memctrl);
}
+unsigned long get_top_of_ram(void)
+{
+ u32 tolm = (pci_read_config16(MCHDEV, TOLM) & ~0x7ff) << 16;
+ return (unsigned long) tolm;
+}
+
/**
* Scrub and reset error counts for ECC dimms.
*
diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h
index 8eb4990364..f9ba7968be 100644
--- a/src/northbridge/intel/e7505/raminit.h
+++ b/src/northbridge/intel/e7505/raminit.h
@@ -20,6 +20,7 @@ void e7505_mch_scrub_ecc(unsigned long ret_addr);
void e7505_mch_done(const struct mem_controller *memctrl);
int e7505_mch_is_ready(void);
+unsigned long get_top_of_ram(void);
/* Mainboard exports this. */
int spd_read_byte(unsigned device, unsigned address);