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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-05-04 21:06:04 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-05 19:39:22 +0000 |
| commit | 144c7aa34bffba7b65566e037f0588ace8b00eba (patch) | |
| tree | c46e83920de270267acb6d3fc750d8b432c89ad7 /src/soc/amd/cezanne/chip.c | |
| parent | afc4978ede7c86cddb0552ebc8da046244affe61 (diff) | |
| download | coreboot-144c7aa34bffba7b65566e037f0588ace8b00eba.tar.xz | |
soc/amd/cezanne/agesa_acpi: add and call agesa_write_acpi_tables
This function will be used to add some SSDTs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia88cb5ea483850a8659f3bae8040c82eb2735d26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Diffstat (limited to 'src/soc/amd/cezanne/chip.c')
| -rw-r--r-- | src/soc/amd/cezanne/chip.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index 8625bd75f1..625f46ce8e 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -4,6 +4,7 @@ #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> +#include <soc/acpi.h> #include <soc/cpu.h> #include <soc/data_fabric.h> #include <soc/pci_devs.h> @@ -79,6 +80,8 @@ static void enable_dev(struct device *dev) static void soc_init(void *chip_info) { + default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; + fsp_silicon_init(); data_fabric_set_mmio_np(); |