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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-07-24 19:10:03 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-07-27 18:42:14 +0000 |
| commit | bcb3d0397303272ed201f46bb41c4d029f384fa1 (patch) | |
| tree | 1e722a1e32bf940ab90146f92e47f0e876bd36cd /src/soc/amd/picasso/chip.h | |
| parent | 1e5edb48c3dc66ef73a43413a27baff5a43ef268 (diff) | |
| download | coreboot-bcb3d0397303272ed201f46bb41c4d029f384fa1.tar.xz | |
soc/amd/picasso: make USB over-current pin mapping configurable
Neither the family 17h model 10-1Fh PPR nor the internal FSP source
seems to have the mapping of the USB OC pins to the four bit values, so
this is based on the information from the family 15h model 70-7Fh BKDG
which also corresponds to what I'd have expected here.
BUG=b:162010077
Change-Id: I581ef1d730e9d729d9849d7e73ef1c1b67b2c4cf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/picasso/chip.h')
| -rw-r--r-- | src/soc/amd/picasso/chip.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 64258b24ca..62272c0927 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -137,6 +137,15 @@ struct soc_amd_picasso_config { uint8_t has_usb2_phy_tune_params; struct usb2_phy_tune usb_2_port_tune_params[USB_PORT_COUNT]; + enum { + USB_OC_PIN_0 = 0x0, + USB_OC_PIN_1 = 0x1, + USB_OC_PIN_2 = 0x2, + USB_OC_PIN_3 = 0x3, + USB_OC_PIN_4 = 0x4, + USB_OC_PIN_5 = 0x5, + USB_OC_NONE = 0xf, + } usb_port_overcurrent_pin[USB_PORT_COUNT]; }; typedef struct soc_amd_picasso_config config_t; |