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authorAaron Durbin <adurbin@chromium.org>2018-01-24 17:42:51 -0700
committerAaron Durbin <adurbin@chromium.org>2018-01-25 23:30:14 +0000
commit51e4c1a76cafa0ddd429ffa78d0e6fdee179f731 (patch)
tree1c540ebc0ba5a94ed9119b02be2e985597e5c2f9 /src/soc/amd/stoneyridge/Kconfig
parentf49ddb67de5b6ff86ad080585bd835779521d647 (diff)
downloadcoreboot-51e4c1a76cafa0ddd429ffa78d0e6fdee179f731.tar.xz
soc/amd/stoneyridge: remove dependence on TSC
The TSC rate is empirically swinging during early boot. That leaves timestamps and udelay()s to not be correct. To rectify this stop using TSC for all of these time sources. Instead use the performance TSC which is at a fixed 100MHz clock. That provides stable time sources and legit timestamps. BUG=b:72378235,b:72170796 Change-Id: Ia2693c415c557aac687bcb48ee69358ea1c53d67 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/Kconfig')
-rw-r--r--src/soc/amd/stoneyridge/Kconfig4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index fbeabb71cd..148ca3ff04 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -32,14 +32,14 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ACPI_AMD_HARDWARE_SLEEP_VALUES
+ select COLLECT_TIMESTAMPS_NO_TSC
select DRIVERS_I2C_DESIGNWARE
select GENERIC_GPIO_LIB
+ select GENERIC_UDELAY
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_HARD_RESET
- select UDELAY_TSC
select HAVE_MONOTONIC_TIMER
- select TSC_CONSTANT_RATE
select SPI_FLASH if HAVE_ACPI_RESUME
select TSC_SYNC_LFENCE
select COLLECT_TIMESTAMPS