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authorRaul E Rangel <rrangel@chromium.org>2021-04-26 13:52:38 -0600
committerMartin Roth <martinroth@google.com>2021-04-29 15:36:00 +0000
commit01792e353b62ef8d7e9bea7e42e7449d3120aab8 (patch)
treec2fcb87e078fcc98337d420ddba8d3fc15580c37 /src/soc/amd
parent5db62ef94aaa6d9aa1b4d56494a5e95f06d5eb2e (diff)
downloadcoreboot-01792e353b62ef8d7e9bea7e42e7449d3120aab8.tar.xz
soc/amd/common: Remove eSPI decode workaround
We no longer lock up if we clear the port 80 bit. I'm assuming this was fixed when we configured the PSP to no longer setup eSPI. BUG=b:183974365 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1530d08974d42e0b06eb783521dea32fca752d85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/common/block/lpc/espi_util.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index 82f2a85b1c..7752eb5670 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -103,11 +103,7 @@ static void espi_clear_decodes(void)
unsigned int idx;
/* First turn off all enable bits, then zero base, range, and size registers */
- /*
- * There is currently a bug where the SMU will lock up at times if the port80h enable
- * bit is cleared. See b/183974365
- */
- espi_write16(ESPI_DECODE, (espi_read16(ESPI_DECODE) & ESPI_DECODE_IO_0x80_EN));
+ espi_write16(ESPI_DECODE, 0);
for (idx = 0; idx < ESPI_GENERIC_IO_WIN_COUNT; idx++) {
espi_write16(ESPI_IO_RANGE_BASE(idx), 0);