coreboot - Some coreboot project code with my work

Age	Commit message (Expand)	Author
2021-05-21	soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driver	Felix Held
2021-05-20	soc/amd/common: Show espi init in log	Martin Roth
2021-05-19	soc/amd/common/block/espi_util: Work around in-band reset race condition	Raul E Rangel
2021-05-19	soc/amd/cezanne/fch: add PCIe GPP clock generator configuration settings	Felix Held
2021-05-19	soc/amd/picasso: move gpp_clk_req_setting definition to chip.h	Felix Held
2021-05-18	cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y	Arthur Heymans
2021-05-16	soc/amd/*/Makefile.inc: Strip the quotes	Zheng Bao
2021-05-14	soc/amd/cezanne: Enable GFX HDA FSP UPD	Karthikeyan Ramasubramanian
2021-05-13	soc/amd: factor out acpigen_write_alib_dptc to common code	Felix Held
2021-05-13	soc/amd/cezanne/root_complex: generate DPTC ACPI method	Felix Held
2021-05-12	soc/amd/cezanne/chip.h: add DPTC and tablet mode options	Felix Held
2021-05-12	psp_verstage: remove not-implemented files for cezanne	Kangheui Won
2021-05-12	soc/amd/{common,picasso}: Use common PCIE_GPP_DRIVER driver	Raul E Rangel
2021-05-12	soc/amd/common/block/pci: Capitalize PCI ACPI names	Raul E Rangel
2021-05-12	soc/amd{common,cezanne}: Move pcie_gpp.c to common	Raul E Rangel
2021-05-11	soc/amd/picasso: Disable CBFS MCACHE again	Raul E Rangel
2021-05-10	soc/amd/picasso: move acpigen_dptc_call_alib to new common alib	Felix Held
2021-05-10	Revert "soc/amd/common/espi: Don't set alert pin in espi_set_initial_config"	Raul E Rangel
2021-05-10	soc/amd/cezanne: Force resets to be cold	Marshall Dawson
2021-05-10	cezanne/psp_verstage: update SRAM address	Kangheui Won
2021-05-10	amd/cezanne: verify transfer buffer in bootblock	Kangheui Won
2021-05-10	psp_verstage: differentiate bios entry	Kangheui Won
2021-05-10	psp_verstage: move platform-specific code to chipset.c	Kangheui Won
2021-05-10	cezanne/psp_verstage: clean up duplicated target	Kangheui Won
2021-05-10	cezanne/psp_verstage: populate a/b firmware	Kangheui Won
2021-05-09	soc/amd/cezanne: Generate PCI GPP ACPI names	Raul E Rangel
2021-05-09	soc/amd/cezanne: Enable GNB IO-APIC _PRT	Raul E Rangel
2021-05-09	soc/amd/cezanne: add GNB IOAPIC support	Felix Held
2021-05-09	soc/amd/cezanne: Generate PCI routing table	Raul E Rangel
2021-05-09	soc/amd/cezanne: Populate PCI_INTR registers	Raul E Rangel
2021-05-09	soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table	Raul E Rangel
2021-05-09	soc/amd/picasso/pci_gpp: Switch to using acpigen_write_pci_GNB_PRT	Raul E Rangel
2021-05-09	soc/amd/common/block/pci: Implement acpigen_write_pci_{GNB,FCH}_PRT	Raul E Rangel
2021-05-09	soc/amd/{picasso,common/blocks/pci}: Move populate_pirq_data	Raul E Rangel
2021-05-09	soc/amd/picasso: Migrate to struct pci_routing_info	Raul E Rangel
2021-05-09	soc/amd/common/block/pci: Introduce struct pci_routing_info	Raul E Rangel
2021-05-08	soc/amd/cezanne/acpi/soc: call WAL1 for AC/DC state ALIB call	Felix Held
2021-05-08	soc/amd/picasso/acpi/cpu: move WAL1 method that calls ALIB to common	Felix Held
2021-05-08	soc/amd/picasso,common: move ALIB DPTC parameter struct to common code	Felix Held
2021-05-08	soc/amd/picasso,common: move ALIB DPTC IDs to common code	Felix Held
2021-05-08	soc/amd/picasso/root_complex: move DPTC_TOTAL_UPDATE_PARAMS out of enum	Felix Held
2021-05-08	soc/amd: factor out ACPI ALIB function numbers to common code	Felix Held
2021-05-07	soc/amd/common/acpi/pci_int.asl: Allow IRQ sharing	Raul E Rangel
2021-05-07	soc/amd/common: Add Kconfig/Makefile support for common/fsp/*	Raul E Rangel
2021-05-06	soc/amd/common/espi,mb/: Allow configuring open drain ALERT#	Raul E Rangel
2021-05-06	soc/amd/common/espi: Don't set alert pin in espi_set_initial_config	Raul E Rangel
2021-05-06	soc/amd/common/espi: Print set eSPI peripheral config	Raul E Rangel
2021-05-06	soc/amd/{common/picasso}: Move pci_int.asl	Raul E Rangel
2021-05-06	soc/amd/{picasso/common}: Move populate_pirq_data prototype to common	Raul E Rangel
2021-05-05	soc/amd/cezanne/agesa_acpi: add add_agesa_fsp_acpi_table call	Felix Held