soc/amd/cezanne: add remaining non-ACPI parts of UART support

The ACPI part still needs some more code to be in place, so add that
later.

TEST=Together with the currently not merged rest of the amdfw patch
train applied this results in working serial console in bootblock in
Majolica.

Change-Id: Ia844e86a80c19026ac5b47a5a1e91c2553ea5cca
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49378
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 35 insertions, 0 deletions

diff --git a/src/soc/amd/cezanne/uart.c b/src/soc/amd/cezanne/uart.c
index 02a6d22b09..84f7c40078 100644
--- a/src/soc/amd/cezanne/uart.c
+++ b/src/soc/amd/cezanne/uart.c
@@ -1,8 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/aoac.h>
 #include <amdblocks/gpio_banks.h>
 #include <amdblocks/uart.h>
 #include <commonlib/helpers.h>
+#include <console/console.h>
+#include <device/device.h>
 #include <device/mmio.h>
 #include <soc/gpio.h>
 #include <soc/southbridge.h>
@@ -43,3 +46,35 @@ void set_uart_config(unsigned int idx)
 
 	program_gpios(uart_info[idx].mux, 2);
 }
+
+/* Even though this is called enable, it gets called for both enabled and disabled devices. */
+static void uart_enable(struct device *dev)
+{
+	unsigned int dev_id;
+
+	switch (dev->path.mmio.addr) {
+	case APU_UART0_BASE:
+		dev_id = FCH_AOAC_DEV_UART0;
+		break;
+	case APU_UART1_BASE:
+		dev_id = FCH_AOAC_DEV_UART1;
+		break;
+	default:
+		printk(BIOS_ERR, "%s: Unknown device: %s\n", __func__, dev_path(dev));
+		return;
+	}
+
+	if (dev->enabled) {
+		power_on_aoac_device(dev_id);
+		wait_for_aoac_enabled(dev_id);
+	} else {
+		power_off_aoac_device(dev_id);
+	}
+}
+
+struct device_operations cezanne_uart_mmio_ops = {
+	.read_resources = noop_read_resources,
+	.set_resources = noop_set_resources,
+	.scan_bus = scan_static_bus,
+	.enable = uart_enable,
+};