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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2021-04-14 14:08:16 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-16 06:44:36 +0000 |
| commit | a0d48096ad83813d959886ba354f7b7eb0aea179 (patch) | |
| tree | e29c99197a7b0b7131549233869c4ea72cb3479c /src/soc/amd | |
| parent | 6935350ad6610fca943afc4ae96125760538f98c (diff) | |
| download | coreboot-a0d48096ad83813d959886ba354f7b7eb0aea179.tar.xz | |
mb/google/brya: Configure TCSS OC pins for brya
TCSS OC pins has not been correctly configured for brya.
This patch fills the value from devicetree to correct the OC pins
mapping
BUG=b:184653645
BRANCH=None
TEST=check if UPD value has been reflected correctly
Change-Id: Ia21cdbf5768ad7516ea52bff7e247291a7d2ebd1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/soc/amd')
0 files changed, 0 insertions, 0 deletions